1. Field of the Invention
The present invention relates to register transfer level (RTL) simulation, and in particular to a technique of incorporating multi-cycle path information during RTL simulation.
2. Related Art
Some combinational paths of an integrated circuit (IC) design are multi-cycle, i.e. the transition from the source is not supposed to reach the destination in one cycle. In general, multi-cycle paths are due to implementation constraints, e.g. user directives to a tool indicating specific delays for specific paths in the design. In other words, the user may indicate that a specific source may take up to a set number of cycles (e.g. 2, 3, or 4 cycles) to send its value to a specific destination via a specific path. The number of delay cycles set by the user may be due to the type of and/or amount of intervening combinational logic present in the path.
These multi-cycle paths are provided in sideband files as design constraint commands to the synthesis tool, which generates a gate/netlist level description, and the timing analysis tool for use during timing analysis to verify timing constraints. Note that the code input to the synthesis and timing analysis tool merely provides the combinational logic transfer function between the source and destination for the path connecting that source/destination. However, when synthesis and timing analysis is being performed, the synthesis and timing tool will access the sideband file(s) to ensure that design constraint commands are taken into account.
However, during register transfer level (RTL) simulation (which accesses an RTL description and verifies correct system operation), this information is not used. Specifically, in RTL, all combinational paths are characterized as zero delay, i.e. single cycle. Therefore, the transition on a multi-cycle path reaches the destination in one cycle. Unfortunately, this early transition can lead to incorrect simulation results and can mask design bugs. For example, any design flaw that expects a multi-cycle path to propagate a transition in one cycle will erroneously pass RTL simulation.
These multi-cycle path bugs may be caught later during gate level simulation with detailed timing annotated to the gates. However, this analysis is very late in the design cycle and generally involves expensive iterations of verification, synthesis, and place & route in addition to being very performance intensive and slow. Thus, gate level simulation is commercially impractical to cover more than a handful of multi-cycle path bugs. In the worst case, the multi-cycle path bugs may not be detected until tape out, thereby causing a re-spin of one or more masks.